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march 2016 docid16525 rev 5 1 / 36 this is information on a product in full production. www.st.com STPMS2 smart sensor ii dual - channel 1 - bit, 4 mhz, second - order sigma - delta modulator with embedded pglna datasheet - production data features ? v cc supply range 3.2 v to 5.5 v ? two second - order sigma - delta (?) modulators ? programmable chopper - stabilized low noise and low offset amplifier ? supports 50 - 60 hz, en 50470 - 1, en 50470 - 3, iec 62053 - 21, iec 62053 - 22 and iec 62053 - 23 standard specs for class 1, class 0.5 and class 0.2 ac watt meters ? STPMS2l - pur: less than 0.5% error over 1:5000 range ? precision voltage reference: 1.23 v with programmable tc ? internal low drop regulator @ 3 v (typ.) applications ? p ower metering ? motor control ? industrial process control ? weight scales ? pressure transducers description the STPMS2 also called smart sensor device, is an assp designed for effectiv e measurement in power line systems utilizing the rogowski coil, current transformer and hall or shunt sensors. this device is designed as a building block for single - phase or multi - phase energy meters along with the stpmc1 device, a digital signal process or designed for energy measurement. this device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time. the STPMS2 is a mixed signal ic consisting of an analog and digital section . the analog section consists of a programmable gain, low noise chopper amplifier, two second - order ? modulator blocks, a bandgap voltage reference, a low drop voltage regulator and dc buffers, while the digital section consists of a clock generator and o utput multiplexer. table 1: device summary oder code package packing STPMS2l - pur qfn16 (4x4 mm) 4500 pieces per reel
contents STPMS2 2 / 36 docid16525 rev 5 contents 1 introduction ................................ ................................ ..................... 5 2 internal block diagram ................................ ................................ .... 6 3 pin configuration ................................ ................................ ............. 7 4 maximum ratings ................................ ................................ ............. 8 5 electrical characteristics ................................ ................................ 9 6 applications ................................ ................................ ................... 13 7 terminology ................................ ................................ ................... 16 7.1 conventions ................................ ................................ .................... 16 7.2 notations ................................ ................................ ......................... 16 8 typical performance characteristics ................................ ........... 17 9 theory of operation ................................ ................................ ....... 19 9.1 general operation description ................................ ......................... 19 9.2 functional description of the analog part ................................ ........ 19 9.3 functional description of the digital part ................................ .......... 22 9.3.1 d ecoder for different modes of operations ................................ ....... 23 9.3.2 generator for clock frequency ................................ .......................... 23 9.4 hard mode ................................ ................................ ...................... 24 9.5 soft mode ................................ ................................ ........................ 25 9.5.1 writing to the configuration register in soft mode ............................. 30 10 package information ................................ ................................ ..... 32 10.1 qfn16 (4x4 mm) package information ................................ ........... 33 11 revision history ................................ ................................ ............ 35
STPMS2 list of tables docid16525 rev 5 3 / 36 list of tables table 1: device summary ................................ ................................ ................................ ........................... 1 table 2: pin description ................................ ................................ ................................ .............................. 7 t able 3: absolute maximum ratings ................................ ................................ ................................ ........... 8 table 4: thermal data ................................ ................................ ................................ ................................ . 8 table 5: electrical characteristics ................................ ................................ ................................ ............... 9 table 6: recommended external components in metering applications ................................ .................. 14 table 7: operating modes ................................ ................................ ................................ ........................ 20 table 8: precision mode and input amplifier gain selection ................................ ................................ ..... 24 table 9: tc of the bandgap reference ................................ ................................ ................................ ...... 25 table 10: control of voltage channel and output signals ................................ ................................ .......... 25 table 11: selection of hard, soft or test mode and enable of bist ................................ .......................... 25 table 12: pins for spi communication ................................ ................................ ................................ ...... 26 table 13: descrip tion of output signals and configuration bits cfg[39:0] ................................ ............... 26 table 14: ebistc ................................ ................................ ................................ ................................ ..... 27 table 15: ebistv ................................ ................................ ................................ ................................ ..... 28 table 16: mc[2:0] ................................ ................................ ................................ ................................ ..... 28 table 17: nc[2:0] ................................ ................................ ................................ ................................ ...... 28 table 18: mv[2:0] ................................ ................................ ................................ ................................ ...... 29 table 19: nv[2:0] ................................ ................................ ................................ ................................ ...... 29 table 20: dtmc[5:0] ................................ ................................ ................................ ................................ . 29 table 21: qfn16 (4x4 mm) mechanical data ................................ ................................ ........................... 34 table 22: doc ument revision history ................................ ................................ ................................ ........ 35
list of figures STPMS2 4 / 36 docid16525 rev 5 list of figures figure 1: STPMS2 internal block diagram ................................ ................................ ................................ .. 6 figure 2: pin connections ................................ ................................ ................................ ........................... 7 figure 3: timing diagram ................................ ................................ ................................ .......................... 12 figure 4: detailed application schematic ................................ ................................ ................................ .. 13 figure 5: simplified application schematics for the stpmc1 energy metering - based ............................ 14 figure 6: connection schematics for dsp - based applications ................................ ................................ 15 figure 7: vref/vref at 25 deg vs. temp ................................ ................................ ................................ 17 figure 8: snhr of i channel, gain 16x ................................ ................................ ................................ ..... 17 figure 9: snhr of i channel, gain 2x ................................ ................................ ................................ ....... 17 figure 10: snhr of v channel, gain 2x ................................ ................................ ................................ .... 17 figure 11 : sinad of i channel, gain 16x (temp. variation) ................................ ................................ ....... 17 figure 12: sinad of i channel, gain 2x (temp. variation) ................................ ................................ ......... 17 figure 13: relative gain error of i channel, gain 16x ................................ ................................ ................ 18 figure 14: relative gain error of i channel, gain 2x ................................ ................................ .................. 18 figure 15 : accuracy over dynamic range ................................ ................................ ................................ . 18 figure 16: power supply external connection scheme ................................ ................................ ............. 20 figure 17: block diagram of the modulator ................................ ................................ ............................... 21 f igure 18: example of sigma - delta modulator output in case of sinusoidal waveform ............................ 22 figure 19: block diagram and definition of df e digital signals ................................ ................................ 23 figure 20: timings to switch to soft mode after por ................................ ................................ ............... 30 figure 21: timings to switch to soft mode ................................ ................................ ................................ 31 figure 22: qfn16 (4x4 mm) package outline ................................ ................................ .......................... 33 figure 23: qfn16 (4x4 mm) recommended footprint ................................ ................................ ............... 34
STPMS2 introduction docid16525 rev 5 5 / 36 1 introduction the STPMS2 is a device desig ned to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive rogowski coil, current transformer or shunt resistors). the device is used together with a digital sign al processing circuit to implement an effective measuring system for multi - phase power meters. the device consists of two analog measuring channels, consisting of second - order sigma - delta modulators with an appropriate non - overlapping control signal genera tor. the STPMS2 also includes a temperature compensated bandgap reference voltage generator, a low drop supply voltage stabilizer and a minimal digital circuitry that includes bist (built - in self - test) structures. in a current signal processing channel, a low - noise preamplifier is included in front of the sigma - delta converter. all reference voltages (bandgap, agnd) are internally buffered to eliminate channel crosstalk. the STPMS2 can operate in fast or low - power mode. in fast mode, a nominal clock frequen cy of 4.1 or 4.9 mhz is applied to the clock input. in this mode, signal bandwidth is specified between 0 and 4 khz. in low - power mode, the nominal clock is four times slower in order to reduce the power consumption of the circuit. in low - power mode, the q uiescent bias currents of the preamplifier and sigma - delta integrators are lowered and the signal bandwidth is narrowed to the frequency bandwidth from 0 to 1 khz.
internal block diagram STPMS2 6 / 36 docid16525 rev 5 2 internal block diagram figure 1 : STPMS2 internal block diagram
STPMS2 pin configuration docid16525 rev 5 7 / 36 3 pin configuration figure 2 : pin connections table 2: pin description pin symbol description 1 vcc unregulated supply voltage for pad ring, bandgap, low drop and level shifters 2 vddac current channel modulator supply input 3 vdda output of internal + 3.0 v low drop regulated power supply 4 vbg output of int ernal + 1.23 v bias generator 5 cin current channel - 6 cip current channel + 7 vin voltage channel - 8 vip voltage channel + 9 vddav voltage channel modulator supply input 10 ms0 input for configurator 0 11 ms1 input for configurator 1 12 ms2 inpu t for configurator 2 13 ms3 input for configurator 3 14 clk input for external measurement clock 15 dat output of multiplexed ? signal. output of current ? signal 16 datn output of inverted multiplexed ? signal. output of voltage ? signal 17 gnd g round level for signals and pin protection
maximum ratings STPMS2 8 / 36 docid16525 rev 5 4 maximum ratings table 3: absolute maximum ratings symbol parameter value unit v cc dc input voltage - 0.3 to 6 v i pin current on any pin (sink/source) 150 ma v id input voltage on any pin - 0.3 to v cc +0.3 v v ia input voltage at analog pins (vip, vin, iip, iin) - 0.7 to 0.7 v esd human body model 2 kv t op operating ambient temperature - 40 to 85 c t j maximum operating junction temperature - 40 to150 c t stg storage temperature - 55 to 150 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4: thermal data symbol paramet er value unit r thja (1) thermal resistance junction - ambient 38.66 c/w notes: (1) this value is referred to single - layer pcb, jedec standard test board.
STPMS2 electrical characteristics docid16525 rev 5 9 / 36 5 electrical characteristics v cc = 5 v, t amb = 25 c, 1 f between v cc , vdda, vddac, vddav and gnd, 100 nf between vbg and gnd, f clk = 4.19 mhz unless otherwise specified. table 5: electrical characteristics symbol parameter test c onditions min. typ. max. unit general section v cc operating supply voltage 3.135 5.25 v i cc quiescent current lp, 1.229 mhz; v cc = 3.3 v; cl = 100 nf; no loads 1.2 1.5 ma hp, 4.915 mhz; v cc = 3.2 v; cl =100 nf; no loads 4 5 v por power - on - rese t on v cc 2.5 v v dd regulated supply voltage 1.049 mhz; v cc = 3.2 v; cl = 100 nf; no loads 2.95 3.00 3.05 v i latch current injection latch - up immunity 300 ma f bw effective bandwidth limited by chopper 0 4091 hz dc measurement accuracy resoluti on 11 16 bit inl integral non linearity result referred to a 16 - bit word of cip - cin channel, hp mode, f clk = 2.047 mhz 3.3 lsb result referred to a 12 - bit word of vip - vin channel, hp mode, f clk = 2.047 mhz 3.9 dnl differential linearity result referred to a 16 - bit word of cip - cin channel, hp mode, f clk = 2.047 mhz 0.3 lsb result referred to a 12 - bit word of vip - vin channel, hp mode, f clk = 2.047 mhz 0.5 offset error result referred to a 16 - bit word of cip - cin channel, hp mode, f clk = 2 .047 mhz 0.02 lsb result referred to a 12 bit - word of vip - vin channel, hp mode, f clk = 2.047 mhz 0.005 gain error result referred to a 16 - bit word of cip - cin channel, hp mode, f clk = 2.047 mhz 0.04 0.4 lsb/uv result referred to a 12 - bit word of vip - vin channel, hp mode, f clk = 2.047 mhz 0.003
electrical characteristics STPMS2 10 / 36 docid16525 rev 5 symbol parameter test c onditions min. typ. max. unit nf noise floor cip - cin channel gain 2x 120 db cip - cin channel gain 16x 118 vip - vin channel 95 psrr dc power supply dc rejection voltage signal: 200 mvrms/50 hz current signal: 10 mvrms/ 50 hz f clk = 2.048 mhz v cc = 3.3 v 10%, 5 v 10% 90 db ac measurement accuracy snr signal - to - noise ratio cip - cin channel C vin = 230 mv @ 55 hz gain 2x over 4 khz bandwidth 82 db vip - vin channel C vin = 230 mv @ 55 hz over 4 khz bandwidth 52 sinad signal - to - noise ratio + distortion cip - cin channel C vin = 230 mv @ 55 hz gain 2x over 4 khz bandwidth 82 db vip - vin channel C vin = 230 mv @ 55 hz over 4 khz bandwidth 52 thd total harmonic distortion cip - cin channel C vin = 230 mv @ 55 hz gain 2x over 4 khz bandwidth - 105 db vip - vin channel C vin = 230 mv @ 55 hz over 4 khz bandwidth - 78 sfdr spurious free dynamic range cip - cin channel C vin = 230 mv @ 55 hz gain 2x over 4 khz bandwidth 90 db vip - vin channel C vin = 230 mv @ 55 hz over 4 khz bandwidth 68 psrr ac power supply ac rejection voltage signal: 200 mvrms/50 hz current signal 10 mvrms/50 hz f clk = 2.048 mhz v cc = 3.3 v+0.2 vrms1@100 hz v cc = 5.0 v+0.2 vrms1@100 hz 120 db analog inputs (cip, cin, vip , vin) v max maximum input signal levels vip - vin channel - 0.3 +0.3 v cip - cin channel: gain 2x - 0.3 +0.3 v cip - cin gain 4x - 0.15 +0.15 cip - cin gain 8x - 0.075 +0.075 cip - cin gain 16x - 0.0375 +0.0375 f spl a/d sampling frequency f clk hz
STPMS2 electrical characteristics docid16525 rev 5 11 / 36 symbol parameter test c onditions min. typ. max. unit v off amplifier offset 20 mv z ip vip, vin impedance over total operating voltage range 100 400 k z in cip, cin impedance over total operating voltage range 35 50 k g err gain error of current channels 10 % i ilv voltage channel leakage curren t v cc = 5.25 v, f clk = 4.19 mhz - 1 1 a i ili current channel leakage current v cc = 5.25 v, f clk = 4.19 mhz - 1 1 a v cc = 5.25 v, f clk = 4.19 mhz input enabled - 10 10 a crosstalk between channels 130 db digital i/o (clk, dat, datn, ms0, ms1, m s2, ms3) v ih input high voltage 0.75 v cc 5.3 v v il input low voltage - 0.3 0.25 v cc v v oh output high voltage i o = - 1 ma, cl = 50 pf, v cc = 3.2 v v cc - 0.4 v v ol output low voltage i o = +1 ma, cl = 50 pf, v cc = 3.2 v 0.4 v i up pull - up current 15 a t tr transition time c load = 50 pf 10 ns t l latency from 50% of clk to 50% to dat 40 ns clock input f clk nominal frequencies low precision mode 1.0 1.228 mhz high precision mode 2.0 2.458 high precision mode 4.0 4.915 on - chip referenc e voltage v ref reference voltage 1.21 1.23 1.25 v z out output impedance 30 200 k i l maximum load current 0 a t c temperature coefficient after calibration 30 50 ppm/c
electrical characteristics STPMS2 12 / 36 docid16525 rev 5 figure 3 : timing diagram clk - clock signal on clk pin clk sample - sigma - delta sampling frequency bsv - sigma - delta bit stream of voltage signal bsc - sigma - delta bit stream of current signal data - multiplexed data of voltage and current signal on dat pin
STPMS2 applications docid16525 rev 5 13 / 36 6 applications the choice of external components is a crucial point in the application design, affecting the precision and the resolution of the entire system. among the several considerations, a compromise should be found among the following requirements: 1. maximize the signal - to - noise ratio in the voltage and current channel. 2. choose the current - to - voltage conversion ratio k s and the voltage divider ratio so that calibration can be achieved. 3. choose k s to take advantage of t he whole current dynamic range in accordance with the desired maximum current and resolution. to maximize the signal - to - noise ratio of the current channel, the voltage divider resistor ratio should be as close as possible to those shown in table 6 . figure 4 below provides a reference application schematic diagram: ? p = 64000 imp/kwh ? i nom = 5 a ? i max = 60 a typical sensitivity values for the current sensors are indicated in table 6: "recommended external components in metering applications" . figure 4 : detailed application schematic
applications STPMS2 14 / 36 docid16525 rev 5 table 6: recommended external components in metering applications function component description value tolerance unit calculator stpmc1 line voltage interface resistor divider r - to - r ratio v rms = 230 v 1:1650 1% 50 ppm/c v/v r - to - r ratio v rms = 110 v 1:830 line current interface rogowski coil current - to - voltage ratio k s 0.15 5% 50 ppm/c m v/a ct 1.7 shunt 0.43 above listed components refer to a typical metering application. the STPMS2 operation is not limited to the choice of these external components. figure 5 : simplified application schematics f or the stpmc1 energy metering - based
STPMS2 applications docid16525 rev 5 15 / 36 figure 6 : connection schematics for dsp - based applications
terminology STPMS2 16 / 36 docid16525 rev 5 7 terminology 7.1 conventions the lowest analog and digital power supply voltage is called gnd, which represents the system ground. all voltage specifications for digital input/output pins are referred to gnd. the highest power supply voltage is called v cc . the highest core power supply is internally generated and is called v dd . positive currents flow into a pin. sinking current means that the current flows into the pin and thus it is positive. sourcing current means that the current f lows out of the pin and thus it is negative. a positive logic convention is used in all equations. 7.2 notations output bit streams of the modulator are indicated as bsv and bsc for voltage and current channels, respectively.
STPMS2 typical perfor mance characteristics docid16525 rev 5 17 / 36 8 typical performance characteristics figure 7 : vref/vref at 25 deg vs. temp figure 8 : snhr of i channel, gain 16x figure 9 : snhr of i channel, gain 2x figure 10 : snhr of v channel, gain 2x figure 11 : sinad of i channel, gain 16x (t emp. variation) figure 12 : sinad of i channel, gain 2x (temp. variation)
typical performance characteristics STPMS2 18 / 36 docid16525 rev 5 figure 13 : relative gain error of i channel, gain 16x figure 14 : relative gain error of i channel, g ain 2x figure 15 : accuracy over dynamic range
STPMS2 theory of operation docid16525 rev 5 19 / 36 9 theory of operation 9.1 general operation description the STPMS2 performs the second - order analog modulation of two channels in parallel, with appropriate non - overlapping control signal generator, of signals with frequencies varying from dc to 4 khz on two independent channels in parallel. the outputs of the converters provide two digital streams of ones and zeroes, which can be then multiplexed to reduce the number of external connections. the STPMS2 converts analog signals on two independent channels i n parallel via delta - sigma (?) analog - to - digital converters into a binary stream of sigma - delta signals. the device is particularly suitable to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divid er) and current sensors (inductive rogowski coil, current transformer or shunt resistors). there is a current channel for line current and a voltage channel for line voltage. the current channel input is connected through an external anti - aliasing rc filte r to a rogowski coil, current transformer (ct) or shunt current sensor which converts line current into an appropriate voltage signal. the current channel includes a low - noise voltage preamplifier with programmable gain. the voltage channel is connected di rectly through a resistor voltage divider and anti - aliasing filter to a line voltage modulator (adc). both channels have quiescent zero signal point at gnd, so the STPMS2 is able to sample differential signals on both channels with their zero point around gnd. the converted ? signals are multiplexed so to reduce the number of external connections. the conversion and the multiplex are driven by external clock signal clk. the device is used with a digital signal processing circuit to implement a measuring sy stem of a multi - phase power meter. the STPMS2 also includes a temperature compensated bandgap reference voltage generator, low drop supply voltage regulator and minimal digital circuitry that includes bist (built - in self - test) structures. in a current sign al processing channel, a low - noise preamplifier is included upstream of the sigma - delta converter. all reference voltages are designed to eliminate channel crosstalk. the STPMS2 can operate in fast (hp) or low - power (lp) mode (see also table 7 ). in fast mode, a nominal clock frequency of 4.1 or 4.9 mhz is applied to the clock input. in this mode, signal bandwidth is specified between 0 and 4 khz. in low - power mode, the nominal clock is four times slower (1 mhz) to lower the power consumption of the circuit. in low - power mode, the quiescent bias currents of the preamplifier and sigma - delta integrators are reduced and the signal bandwidth is narrowed to the frequency bandwidth from 0 to 1 khz. the mode of operation and configur ation of the device can be selected by wiring configuration pins (ms0, ms1, ms2 and ms3) to vcc, gnd, clk or nclk signal. this approach can be used to change the settings of a current channel, sigma - delta stream output mode and temperature compensation cur ve of an internal bandgap reference. these pins can act as a serial port to change the configuration of the device. 9.2 functional description of the analog part the supply pins for the analog part are vcc, vdda, vddac, vddav, vbg and gnd. the gnd pin also represents a reference point. the vdda is an analog i/o pin of the internal +3.0 v low drop voltage regulator and the vddac and vddav are the modulat or supply in puts. a capacitor of 1 f should be connected between vddxx and gnd. the input of the regulator is vcc, which also powers the bandgap and bias generators. the bandgap output pin is vbg, which should be connected to gnd via a capacitor of 100 nf.
theory of operation STPMS2 20 / 36 docid16525 rev 5 figure 16 : power supply external connection scheme the analog part of the STPMS2 consists of: ? preamplifier in the current channel ? 1.23 v reference voltage generator ? +3 v low drop supply voltage regulator ? two sigma - delta 2 nd order modul ators ? bist dac ? agnd and v ref reference buffers ? bias current generators the voltage channel has a preamplification gain of 2, which defines the maximum differential voltage on voltage channel inputs to 300 mv. the relative gain of the current channel is s electable among 2, 4, 8 or 16, which defines the maximum differential voltage on the current channel to 300 mv, 150 mv, 75 mv or 37.5 mv, respectively. the full range of gains is available in soft mode only, while in hard mode 2 and 16 are the only selectable. the temperature - compensated reference voltage generator produces v ref = 1.23 v. this generator is implemented as a bandgap generator, whose temperature compensation curve can be selected through configuration. the low drop regulator fixes and stabilizes the core supply voltage to vdda = 3 v. all digital pads tolerate 5 v logic levels. the STPMS2 is clocked by an external clock signal connected to pin clk. the STPMS2 sigma - delta modulators work in several operating modes, shown in table 7: "operating modes" below. table 7: operating modes operating mode f clk current consumption lp (low power) lpr (low precision) 1 mhz 1.2 ma typ. hp (fast) hpr (high precision) 2 mhz C 4 mhz 4 ma typ.
STPMS2 theory of operation docid16525 rev 5 21 / 36 lpr (low precision): f clk = 1 mhz and settings defined by ms0 through ms3 hpr (high precision): the normal mode of operation with f clk = 2 mhz to 4 mhz the STPMS2 performs operations in 2 basic modes: hard mode and soft mode. in hard mode the configuration is set through external pins ms0, ms1, ms2 and ms3. in soft mode, 40 configuration bits can be accessed through cfg[39:0], via serial communication. the pins used for serial communication are: ms0, ms1 and ms2. switching between hard and soft mode is achieved through pin ms3. ? h ard mode: in this case the device configuration is bootstrapped at startup and signals come from vin and vip for voltage channels, and cip and cin for current channels or from internal bist dac. ? soft mode: in this mode all possible settings from hard mode are accessible, as well as the additional settings. figure 17 : block diagram of the modulator the STPMS2 sends selected signals based on the configuration to the dat and datn pins. both outputs have cross - current and slew rate li miters to prevent excessive current spikes on supply lines.
theory of operation STPMS2 22 / 36 docid16525 rev 5 figure 18 : example of sigma - delta modulator output in case of sinusoidal waveform 9.3 functional description of the digital part the digital section (dfe) includes: ? a decoder for different modes of operation ? a generator for clock frequency ? level shifters, pull - up stages and power buffers outside the dfe block
STPMS2 theory of operation docid16525 rev 5 23 / 36 figu re 19 : block diagram and definition of dfe digital signals 9.3.1 decoder for different modes of operations the decoder defi nes the operating mode according to the state of the bootstrap ms0, ms1, ms2 and ms3 pins. two different operational modes can be defined: ? hard mode: in this case the device configuration is bootstrapped at startup and signals come from vin and vip for vol tage channels, and cip and cin for current channels or from internal bist dac. ? soft mode: in this mode all possible settings from hard mode are accessible, as well as additional settings such as dither and chopper signal frequencies and operation. 9.3.2 generato r for clock frequency chopper and bist frequency generator the chopper block generates the chopper frequencies and bist signals for the voltage and current channels. the bist dac output levels are appropriately adjusted for the current channel according to the gain selection, while for the voltage channel the max. dc voltage is used. the levels are 300 mv for the voltage channel and 300 mv / 150 mv / 75 mv / 37.5 mv for the current channel, in accordance with gain settings 2/4/8/16, respectively in soft mode, while 300 mv / 37.5 mv based on gain settings 2/16 in hard mode. pseudo random the pseudo random block generates pseudo random signals for the voltage and current channels. these random signals are used to implement a dithering technique to decorrelate the output of the modulators and avoid accumulation points on the frequency spectrum.
theory of operation STPMS2 24 / 36 docid16525 rev 5 synchro in synchro block the synchronization of sigma - delta input streams with strobe signals from analog part and clock signal is performed. mux in the mux block signals, connected to output pins dat and datn, are selected. in hard mode, the output signals are selected by input pin ms2. in soft mode, the output signal s are selected by 8 configuration bits. 9.4 hard mode the STPMS2 works in hard mode when input pin ms3 is connected to gnd or vcc, as described in tab le 11 . in hard mode, the STPMS2 has four digital input pins (ms0, ms1, ms2 and ms3) to configure the basic operating parameters: ? bist dac enable ? temperature curve of reference voltage ? current and voltage channel settings ? output mode settings in this mann er, 128 different combinations are available and they are controlled by ms0, ms1, ms2 and ms3 pins. ms0 sets the operating mode and amplifier gain selection as described in table 8: "precision mode and input amplifier gain s election" . ? ms0 = gnd or clk to select lpr (low precision); f clk = 1 mhz is the typical input clock frequency and low power mode is selected. ? ms0 = nclk or vcc to select hpr (high precision); f clk = 2 or 4 mhz are the typical input clock frequencies and accuracy is enhanced. the relative gain of the current channel is selectable between 2 or 16, which defines the maximum differential voltage on the current channel to 300 mv or 37.5 mv, respectively. the voltage channel gain setting is fixed at 2, whic h defines the maximum differential voltage on the voltage channel inputs to 300 mv. table 8: precision mode and input amplifier gain selection ms0 mode description gnd 0 lpr, amplifier gain selection g3 = 16 clk 1 lpr, amplifier gain selection g0 = 2 nclk 2 hpr, amplifier gain selection g0 = 2 vcc 3 hpr, amplifier gain selection g3 = 16 ms1 defines the temperature compensation (tc) curve of the internal voltage reference of the STPMS2, as described in table 9: "tc of the bandgap reference" (characterized by application). the temperature - compensated reference voltage generator produces v ref = 1.23 v. this generator is implemented as a bandgap generator, whose temperature compensation curve can be selected by ms1 config uration pin.
STPMS2 theory of operation docid16525 rev 5 25 / 36 table 9: tc of the bandgap reference ms1 mode description gnd 0 tc = 50 ppm/c clk 1 tc = - 140 ppm/c nclk 2 tc = 130 ppm/c vcc 3 tc = - 40 ppm/c ms2 defines the outputs of the device. the STPMS2 sends the sigma - delta stream synchrono us to the clk signal. the output mode can be configured according to table 10: "control of voltage channel and output signals" as follows: ? sigma - delta stream of the output current channel on dat and the sigma - delta stream of the voltage channel on datn. ? output multiplexed signals, so when clk = 0, the current channel output sigma - delta value is set on the dat pin, and when clk = 1, the voltage channel output sigma - delta value is set on the dat pin. the datn pin tracks dat, so datn = ~dat. ? sigma - delta stream of the output current channel on dat and the sigma - delta stream of the current channel negated on datn. table 10: control of voltage channel and output signals ms2 mode description gnd 0 voltage channel on, datn = ~ [dat =(clk) ? bsv : bsc)] clk 1 voltage channel off, datn = bscn, dat = bsc nclk 2 voltage channel off, datn = bscn, dat = bsc vcc 3 voltage channel on, datn = bsc, dat = bsv ms3 enables or disables the bist dac output levels. if enabled (ms3=vcc), the in put of the modulators, disconnected from vip pin, vin, cip and cin, and connected to the output of bist dac, generates 2 different levels appropriately adjusted for the current channel 300 mv / 37.5 mv depending on gain settings 2/16, while for the voltage channel, 300 mv is used. this mode is used as auto diagnostic methodology of good behavior of the two modulators. when disabled (ms3=gnd), the input of the modulators comes from pins vip, vin, cip and cin. this is the normal operating condition. table 11: selection of hard, soft or test mode and enable of bist ms3 mode description gnd 0 hard mode, bist mode off clk 1 soft mode nclk 2 reserved vcc 3 hard mode, bist mode on 9.5 soft mode the STPMS2 switches to soft mode when ms3 is connected to clk. in soft mode, input pins (ms0, ms1 and ms2) control the serial communication port, as described in table 12: "pins for spi communication" . all settings of the 40 internal configuration bits can be changed. the old values remain in the registers until they are overwritten.
theory of operation STPMS2 26 / 36 docid16525 rev 5 table 12: pins for spi communication pin function description ms0 scl clock input ms1 tdi data input ms2 tds enable ms3 clk spi op eration table 13: description of output signals and configuration bits cfg[39:0] hard mode soft mode internal signal description ms0 cfg[0] lp/hp operating mode: lp/hp=0: lpr lp/hp=1: hpr ms0 cfg[1] gain gain selector of current channel preamplifier: gain=0: x2 gain=1: x4 gain=2: x8 gain=3: x16 ms0 cfg[2] ms1 cfg[3] tc temperature compensation of voltage reference: tc=0: 50 ppm/c tc=1: - 140 ppm/c tc=2: 130 ppm/c tc=3: - 40 ppm/c ms1 cfg[4] ms2 cfg[5] domul output multiplexer enable: do mul=0: outputs not multiplexed domul=1: outputs multiplexed ms2 cfg[6] pdv power - down of voltage modulator: pdv=0: voltage modulator on pdv=1: voltage modulator off ms3 cfg[7] ebistc current modulator bist dac enable: ebistc=0: bistc disabled ebistc=1: bistc enabled please see table 14: "ebistc" for details ms3 cfg[8] ebistv voltage modulator bist dac enable: ebistc=0: bistv disabled ebistc=1: bistv enabled please, see table 15: "ebistv" for details ms3 cfg[9] einchpc cip, cin input pin enable: einchpc=0: cin cip disabled einchpc=1: cin cip enabled ms3 cfg[10] einchpv vip, vin input pin enable: einchpc=0: vin vip disabled einchpc=1: vin vip enabled 1 cfg[11] echplfc low frequency chopp er of current modulator enable: echplfc=0: lfc disabled echplfc=1: lfc enabled 1 cfg[12] mc lfc of current channel frequency selector. please see table 16: "mc[2:0]" for details 0 cfg[13] 0 cfg[14]
STPMS2 theory of operation docid16525 rev 5 27 / 36 hard mode soft mode internal signal description 1 cfg[15] echphf c high frequency chopper of current modulator enable: echphfc=0: hfc disabled echphfc=1: hfc enabled 1 cfg[16] nc hfc of current channel frequency selector. see table 17: "nc[2:0]" for details 1 cfg[17] 0 cfg[18] 1 cfg[19] echplfv low frequency chopper of voltage modulator enable: echplfv=0: lfv disabled echplfv=1: lfv enabled 1 cfg[20] mv lfc of voltage channel frequency selector. see table 18: "mv[2:0]" for details 0 cfg[21] 0 cfg[22] 1 cfg[23] echphfv high frequency chopper of voltage modulator enable: e chphfc=0: hfv disabled echphfc=1: hfv enabled 1 cfg[24] nv hfc of voltage channel frequency selector. see table 19: "nv[2:0]" for details 1 cfg[25] 0 cfg[26] 1 cfg[27] eprsc current modulator pseudo random signals enable: eprsc=0: prsc disabled eprsc=1: prsc enabled 1 cfg[28] eprsv voltage modulator pseudo random signals enable: eprsv=0: prsv disabled eprsv=1: prsv enabled 0 cfg[29] - reserved 0 cfg[30] - reserved 0 cfg[31] - reserved 0 cfg[32] dtmc dat and dat output signal selector. see table 20: "dtmc[5:0]" for details 0 cfg[33] 0 cfg[34] 0 cfg[35] 0 cfg[36] 0 cfg[37] 0 cfg[38] - reserved 0 cfg[39] - reserved table 14: ebistc ebistc frequency output 0 0 1 clk/2 15 x lfc
theory of operation STPMS2 28 / 36 docid16525 rev 5 table 15: ebistv ebistv frequency output 0 0 1 clk/2 15 x lfv table 16: mc[2:0] mc[2:0] frequency 00 0 clk/1024 001 clk/512 010 clk/256 011 clk/128 100 clk/64 101 (1) clk/64 110 (1) clk/64 111 (1) clk/64 notes: (1) combinations are not used. tab le 17: nc[2:0] nc[2:0] frequency 000 (1) clk/256 001 (1) clk/128 010 clk/256 011 clk/128 100 clk/64 101 clk/32 110 clk/16 111 clk/8 notes: (1) combinations are not used.
STPMS2 theory of operation docid16525 rev 5 29 / 36 table 18: mv[2:0] mv[2:0] frequency 000 clk/1024 001 clk/512 010 clk/256 011 clk/128 100 clk/64 101 (1) clk/64 110 (1) clk/64 111 (1) clk/64 notes: ( 1) combinations are not used. table 19: nv[2:0] nv[2:0] frequency 000 (1) clk/256 001 (1) clk/128 010 clk/256 011 clk/128 100 clk/64 101 clk/32 110 clk/16 111 clk/8 notes: (1) co mbinations are not used. table 20: dtmc[5:0] dtmc[5:0] pdv domul dat datn 00xxxx 0 0 bsv bsc 00xxxx 0 1 (bsv,bsc) (bsvn,bscn) 00xxxx 1 0 bsc bscn 00xxxx 1 1 bsc bscn 01xx00 0 0 bsv lfc 01xx01 0 1 (bsv,bsc) hfc 01xx10 1 0 bsc bistc 01xx11 1 1 bs c prsc 1000xx 0 0 lfv bsc 1001xx 0 1 hfv (bsvn,bscn)
theory of operation STPMS2 30 / 36 docid16525 rev 5 dtmc[5:0] pdv domul dat datn 1010xx 1 0 bistv bscn 1011xx 1 1 prsv bscn 110000 x x lfv lfc 110101 x x hfv hfc 111010 x x bistv bistc 111111 x x prsv prsc 9.5.1 writing to the configuration register in soft mode all 40 configuration bits must be overwritten. figure 20 : timings to switch to soft mode after por in the above figure the reference to delay means that after power - on reset, soft mode is selected (ms3=clk), the bits ms0 .. ms2 must be stable at least 5*clk.
STPMS2 theory of operation docid16525 rev 5 31 / 36 figure 21 : timings to switch to soft mode after switching into soft mode (ms3=clk), th e bits ms0 .. ms2 must be stable at least 2*clk. the same rule applies when switching from soft mode to hard mode: ms0 .. ms2 must be stable at least 2*clk.
package information STPMS2 32 / 36 docid16525 rev 5 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
STPMS2 package information docid16525 rev 5 33 / 36 10.1 qfn16 (4x4 mm) package information figure 22 : qfn16 (4x4 mm) package outline
package information STPMS2 34 / 36 docid16525 rev 5 table 21: qfn16 (4x4 mm) mechani cal data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 b 0.25 0.30 0.35 d 3.90 4.00 4.10 d2 2.50 2.80 e 3.90 4.00 4.10 e 3.90 4.00 4.10 e2 2.50 2.80 e 0.65 l 0.30 0.40 0.50 figure 23 : qfn16 (4x4 mm) recommended footprint 7571203_ a
STPMS2 revision history docid16525 rev 5 35 / 36 11 revision history table 22: document revision history date revision changes 23 - oct - 2009 1 initial release. 06 - jul - 2011 2 document status p romoted from preliminary data to datasheet. 11 - oct - 2011 3 modified: 100 f to 100 nf in the section 9.3 01 - mar - 2016 4 updated table 9: "tc of the bandgap reference". 09 - mar - 2016 5 updated table 8: "precision mode and input amplifier gain selection" , table 9: "tc of the bandgap reference" , table 10: "control of voltage channel and output signals" , table 11: "selection of hard, soft or test mode and enable of bist" .
STPMS2 36 / 36 docid16525 rev 5 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on s t products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assistance or the design of purchasers products. no license, express or implied, to any intellectual prop erty right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st f or such product. st and the st logo are trademarks of st. all other product or service name s are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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